Getting started with Verilog
Module - 1 Verilog: Part-I
What is Verilog Hardware Description Language?
What is the concept of Verilog "Module" and what is the basic syntax of Module definition?
How to specify connectivity and what are variable data types and Net data type?
What is a Register data type and how to specify Constant values?
Module - 2 Verilog: Part-II
What are Parameters?
What are Logic Values, Primitive Gates and how Primitive Tri-State gates are instantiated?
What are some important points to note and what are the various Hardware Modeling Issues?
How the synthesis system will generate a wire for f1?
What are the various Verilog Operators?
Module - 3 Verilog: Part-III
What are the different description Styles in Verilog?
What is the Continuous Assignment Data-flow Style?
What is the Procedural Assignment Behavioral Style?
What is the basic syntax of always block and what are the various sequential statements in Verilog?
What are the examples of combinational and sequential logic (part - 1)?
What are the examples of combinational and sequential logic (part - 2)?
Module - 4 Verilog: Part-IV
What are Blocking and Non-blocking Assignments and their different aspects?
What are the important rules to be followed?
What is an Up-down counter (synchronous clear) and what is the Parameterized design of an N-bit counter?
What is a Ring Counter?
What are "Loop" Statements and how to model memory and its examples?
Module - 5 Verilog: Part-V
How to model Finite State Machines (FSMs)?
What is Moore Machine and its example?
What is a Serial Parity Detector and Mealy Machine and its example?
How to design a Sequence detector for pattern '0110'?
What are the different examples with respect to module?
What is a Top level module?
Module - 6 Verilog: Part-VI
How to model memory and its example?
How to Initialize memory and its example?
What are the different specific examples of Memory Modeling?
What is a Verilog Test Bench and how to write a Testbench and its example?
What is the more complete version its example?
Getting started with Verilog - Final Quiz